Compiler Technology for Two Novel Computer Architectures

نویسندگان

  • Ronald Charles Moore
  • Bernd Klauer
  • Klaus Waldschmidt
چکیده

Before it can achieve wide acceptance, parallel computation must be made significantly easier to program. One of the main obstacles to this goal is the current usage of memory, both abstractly, by programmers, and concretely, by computer architects. In this paper, we present compiler technology for two novel computer architectures, and discuss how, on the one hand, many traditional, memory-based restraints on parallelism can be removed by the compiler — and, on the other hand, how computer architecture (along with appropriate compiler components) can provide a truly transparent virtual distributed memory in such a way so as to move both data-distribution and scheduling into the hardware domain, alleviating the programmer from these concerns.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Novel Multiply-Accumulator Unit Bus Encoding Architecture for Image Processing Applications

In the CMOS circuit power dissipation is a major concern for VLSI functional units. With shrinking feature size, increased frequency and power dissipation on the data bus have become the most important factor compared to other parts of the functional units. One of the most important functional units in any processor is the Multiply-Accumulator unit (MAC). The current work focuses on the develop...

متن کامل

Two Novel D-Flip Flops with Level Triggered Reset in Quantum Dot Cellular Automata Technology

Quantum dot cellular automata (QCA) introduces a pioneer technology in nano scale computer architectures. Employing this technology is one of the solutions to decrease the size of circuits and reducing power dissipation. In this paper, two new optimized FlipFlops with reset input are proposed in quantum dot cellular automata technology. In addition, comparison with related works is performed.Th...

متن کامل

Evaluating OpenMP on Chip MultiThreading Platforms

Recent computer architectures provide new kinds of on-chip parallelism, including support for multithreading. This trend toward hardware support for multithreading is expected to continue for PC, workstation and high-end architectures. Given the need to find sequences of independent instructions, and the difficulty of achieving this via compiler technology alone, OpenMP could become an excellen...

متن کامل

Compiler Technology for Migrating Sequential Code to Multi-threaded Architectures

Executing sequential code in parallel on a multithreaded machine has been an elusive goal for many years. It has recently become quite important due to the widespread introduction of multi-cores in PCs. Automatic multi-threading could not be achieved so far because classic compiler analysis was not powerful enough and program behavior was found to be in many cases input dependent. Run time, spe...

متن کامل

A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips

Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC archite...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1997